Very low power consumption SAR ADC for wireless sensor networks
نویسنده
چکیده
This study aims to design analog-to-digital converter based on successive approximations (SAR ADC), with very low power consumption, in an advanced CMOS technology (28 nm), following the industrial methodologies IC. This project was conducted in partnership with Synopsys, operating at a supply voltage of 0.5 V ± 10% with a resolution of 12 bits and 500 kS/s sampling frequency. Keywords— Analog-to-Digital Converter (ADC), Successive-Approximation Register (SAR), low power consumption, Integrated Circuit (IC).
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